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UNC Graphics & Imaging Analysis Research Cluster
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Invited Speakers
The list of confirmed invited speakers include:
Speaker Biographies Jack Dongarra, University of Tennessee (abstract) Jack Dongarra received a Bachelor of Science in Mathematics from Chicago State University in 1972 and a Master of Science in Computer Science from the Illinois Institute of Technology in 1973. He received his Ph.D. in Applied Mathematics from the University of New Mexico in 1980. He worked at the Argonne National Laboratory until 1989, becoming a senior scientist. He now holds an appointment as University Distinguished Professor of Computer Science in the Electrical Engineering and Computer Science Department at the University of Tennessee, has the position of a Distinguished Research Staff member in the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL), Turing Fellow in the Computer Science and Mathematics Schools at the University of Manchester, and an Adjunct Professor in the Computer Science Department at Rice University. He specializes in numerical algorithms in linear algebra, parallel computing, the use of advanced-computer architectures, programming methodology, and tools for parallel computers. His research includes the development, testing and documentation of high quality mathematical software. He has contributed to the design and implementation of the following open source software packages and systems: EISPACK, LINPACK, the BLAS, LAPACK, ScaLAPACK, Netlib, PVM, MPI, NetSolve, Top500, ATLAS, and PAPI. He has published approximately 200 articles, papers, reports and technical memoranda and he is coauthor of several books. He was awarded the IEEE Sid Fernbach Award in 2004 for his contributions in the application of high performance computers using innovative approaches. He is a Fellow of the AAAS, ACM, and the IEEE and a member of the National Academy of Engineering.
David B. Kirk, NVIDIA (abstract) David Kirk has been NVIDIA's Chief Scientist since January 1997. His contribution includes leading NVIDIA graphics technology development for today’s most popular consumer entertainment platforms. In 2007, Dr. Kirk was elected to the National Academy of Engineering (NAE) for his role in bringing high-performance graphics to personal computers. Election to the NAE is among the highest professional distinctions awarded in engineering. In 2002, Dr. Kirk received the SIGGRAPH Computer Graphics Achievement Award for his role in bringing high-performance computer graphics systems to the mass market. From 1993 to 1996, Dr. Kirk was Chief Scientist, Head of Technology for Crystal Dynamics, a video game manufacturing company. From 1989 to 1991, Dr. Kirk was an engineer for the Apollo Systems Division of Hewlett-Packard Company. Dr. Kirk is the inventor of 50 patents and patent applications relating to graphics design and has published more than 50 articles on graphics technology. Dr. Kirk holds B.S. and M.S. degrees in Mechanical Engineering from the Massachusetts Institute of Technology and M.S. and Ph.D. degrees in Computer Science from the California Institute of Technology.
Charles E. Leiserson, MIT (abstract) Charles E. Leiserson received the B.S. degree in computer science and mathematics from Yale University, New Haven, Connecticut, in 1975 and the Ph.D. degree in computer science from Carnegie Mellon University, Pittsburgh, Pennsylvania, in 1981. In 1981, he joined the faculty of the Massachusetts Institute of Technology, Cambridge, Massachusetts. He currently holds the position of Professor of Computer Science and Engineering in the MIT Department of Electrical Engineering and Computer Science. He leads the Supercomputing Technologies (SuperTech) research group and is member of the Theory of Computation research group in the MIT Computer Science and Artificial Intelligence Laboratory. Prof. Leiserson's research centers on developing theoretical principles of parallel and distributed computing, especially as they relate to engineering reality. Prof. Leiserson pioneered the development of VLSI theory and has written many papers on VLSI algorithms, graph layout, and computer-aided design. His contributions include the divide-and-conquer method of graph layout and the ``retiming'' method for optimizing digital circuitry. Prof. Leiserson has been a leader in the development of parallel computing. As a graduate student at Carnegie Mellon, he wrote the first paper on ``systolic'' architectures with his advisor H.T. Kung. While Corporate Fellow of Thinking Machines Corporation, he designed and led the implementation of the network architecture for the Connection Machine Model CM-5 Supercomputer, which incorporated the ``fat-tree'' interconnection network he developed at MIT. Prof. Leiserson has designed and engineered many parallel algorithms, including ones for matrix linear algebra, graph algorithms, optimization, and sorting. Of particular note, he introduced the notion of ``cache-oblivious'' algorithms, which exploit a hierarchy of processor caches efficiently without any tuning of cache-dependent parameters. Prof. Leiserson's recent research has focused on dynamic multithreaded computing. He developed the first provably good ``work-stealing'' scheduler that guarantees the efficient execution of multithreaded programs. He and his SuperTech research group designed and developed the ``Cilk'' multithreaded programming language, which incorporates work-stealing and vastly simplifies multiprocessor programming. His research team implemented the StarTech, *Socrates, and Cilkchess parallel chess-playing programs, which have won numerous prizes in international competition. A team of Cilk programmers led by Prof. Leiserson won First Prize in the 1998 ICFP Programming Contest sponsored by the International Conference on Functional Programming, in which Cilk was declared to be ``the programming language of choice for discriminating hackers.'' Prof. Leiserson's academic work has won many other awards. His Ph.D. dissertation, Area-Efficient VLSI Computation, which deals with the design of systolic systems and with the problem of determining the VLSI area of a graph, won the ACM Doctoral Dissertation Award in 1982, as well as the Fannie and John Hertz Foundation Doctoral Thesis Prize. In 1985 he received a Presidential Young Investigator Award from the National Science Foundation. His textbook, Introduction to Algorithms, coauthored with Ronald L. Rivest, and Thomas H. Cormen, was named Best 1990 Professional and Scholarly Book in Computer Science and Data Processing by the Association of American Publishers. The textbook, now in its second edition with an additional coauthor, Clifford Stein, has been the leading textbook on computer algorithms for many years and is the second most cited textbook in computer science, according to CiteSeer. Prof. Leiserson is the 28th most cited author in computer science, also according to CiteSeer. Prof. Leiserson is a member of the ACM, IEEE, and SIAM. In 1995-6, he was Shaw Visiting Professor in the Department of Information Systems and Computer Science at the National University of Singapore. He is past Computer Science Program Chair for the Singapore-MIT Alliance, a distance-education initiative in which students in Singapore take MIT classes. He held an Adjunct Professorship at the National University of Singapore for many years and was Director of System Architecture, Director of Research, and Network Architect at Akamai Technologies, Inc. of Cambridge, Massachusetts. A dedicated teacher, Prof. Leiserson has directly supervised 20 Ph.D. students and over 50 Master's and Bachelor's students.
John Manferdelli, Microsoft (abstract) John Manferdelli is a Distinguished Engineer who is working as the general manager of incubation in Craig Mundie.s CTO office. He has also served as a senior researcher, software architect, product unit manager, and general manager. His contributions include the development of the next-generation secure computing base technologies and the rights management capabilities currently integrated into Windows, for which he was the original architect. He also has worked in Microsoft Research and in the SQL Server Group. He joined Microsoft in February 1995 when it acquired his company, Natural Language Inc. based in Berkeley. At Natural Language, Manferdelli was the founder and, at various times vice president of R&D and CEO. He has also worked as a staff engineer at TRW Inc., computer scientist and mathematician at Lawrence Livermore National Laboratory, and principal investigator at Bell Labs. He was an adjunct associate professor at Stevens Institute of Technology and is an affiliate faculty member at the University of Washington. Manferdelli has a bachelor.s degree in physics from Cooper Union for the Advancement of Science and Art and a Ph.D. in mathematics from the University of California, Berkeley.
Chuck Moore, AMD (abstract) Chuck Moore is a Senior Fellow at Advanced Micro Devices, and currently the Chief Engineer of AMD's next-generation processor design. Prior to joining AMD, Moore was a Senior Research Fellow at the University of Texas at Austin where he did research on technology scalable computer architecture. Before then, Moore was a Distinguished Engineer at IBM, where he most recently was the chief engineer on the POWER4 project. While at IBM, he was elected to the IBM Academy of Technology and was named an IBM Master Inventor. Moore has been granted 29 US patents, along with several others pending. He has published numerous conference papers and articles on a wide range of subjects related to computer architecture and design. He is on the editorial board for IEEE Micro magazine, and the program committee for several important industry conferences. Moore holds a master's degree in electrical engineering from the University of Texas at Austin, and a bachelor's degree in electrical engineering from the Rensselaer Polytechnic Institute.
David Patterson, UC-Berkeley (abstract) David A. Patterson has been Professor of Computer Science at the University of California, Berkeley, since 1977, after receiving his A.B., M.S., and Ph.D. from UCLA. He is one of the pioneers of RISC, RAID, and NOW, which are widely used. Past chair of the Computer Science Department at UC-Berkeley and the Computing Research Association, he was elected President of the Association for Computing Machinery (ACM) for 2004 to 2006 and served on the Information Technology Advisory Committee for the U.S. President (PITAC) from 2003 to 2005. He co-authored five books, including two on computer architecture with John L. Hennessy: Computer Architecture: A Quantitative Approach (4 editions, latest is ISBN 0-12-370490-1) and Computer Organization and Design: the Hardware/Software Interface (3 editions; latest is ISBN 1-55860-604-1). They have been widely used as textbooks for graduate and undergraduate courses since 1990. His work has been recognized by about 20 awards for research, teaching, and service, including Fellow of ACM and IEEE and election to the National Academy of Engineering. In 2005 he shared Japan's Computer & Communication award with Hennessy and was named to the Silicon Valley Engineering Hall of Fame. In 2006 he was elected to the American Academy of Arts and Sciences and the National Academy of Sciences and he received the Distinguished Service Award from the Computing Research Association. In 2007 he was named a Fellow of the Computer History Museum. Patterson's current projects are the RAD Lab: Reliable Adaptive Distributed systems, RAMP: Research Accelerator for Multiple Processors, and The Berkeley View on Parallel Computing Research
Stephen S Pawlowski, Intel Corporation (abstract) Stephen S. Pawlowski is an Intel Senior Fellow. He is the Digital Enterprise Group chief technology officer and general manager for Architecture and Planning for Intel Corporation. Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and Itanium™ processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products and prior to his current assignment was the director of Corporate Technology Group's Microprocessor Technology Lab. Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993. Pawlowski holds 56 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.
Daniel A. Reed, UNC-Chapel Hill (abstract) Daniel A. Reed is the director of the Renaissance Computing Institute, a major collaborative venture of the University of North Carolina at Chapel Hill, Duke University, North Carolina State University, and the state of North Carolina. RENCI focuses on finding solutions to complex, multidisciplinary problems, bringing together experts from academia, government and industry and applying world-class computing and technology resources to find innovative solutions to these problems. Dr. Reed also is Chancellor’s Eminent Professor and serves as Senior adviser for Strategy and Innovation to UNC-Chapel Hill Chancellor James Moeser. In that role, he works with the Chancellor and other university administrators and faculty to develop new multidisciplinary research initiatives. Reed came to North Carolina in 2004 and from 2004 through April 2007, he was CIO and Vice Chancellor for Information Technology Services at UNC-Chapel Hill. During that time, he led the effort to integrate campus computing services, helped launch the campus Enterprise Resource Planning (ERP) process, and enhanced services for education, research, administration and outreach. Before coming to North Carolina Reed was at the University of Illinois at Urbana-Champaign, where he led the National Center for Supercomputing Applications (NCSA) and the University of Illinois computer science department during a time when more than $100 million in public and private funds were invested in the campus to create an information technology quadrangle. His research focuses on the design of very high-speed computers and on providing new computing capabilities for scholars in science, medicine, engineering and the humanities. Reed is a member of the President’s Council of Advisors on Science and Technology (PCAST) and the current chair of the Board of Directors of the Computing Research Association (CRA). He served on President Bush's Information Technology Advisory Committee, where he chaired the computational science subcommittee. Reed is a member of the Biomedical Informatics Expert Panel for the National Institutes of Health's National Center and chairs the policy board for the National Energy Research Scientific Computing Center, the Department of Energy's high performance computing center for scientific research. While director of NCSA, he led the National Computational Science Alliance, a nationwide partnership to advance scientific discovery via high performance computing, and was principal investigator and chief architect for the National Science Foundation's TeraGrid project, an effort to build and deploy the world's most comprehensive computing infrastructure for open scientific research.
Vivek Sarkar, Rice University (abstract) Professor Sarkar conducts research in programming languages, program analysis, compiler optimizations and virtual machines for parallel and high performance computer systems. His past projects include the X10 programming language, the Jikes Research Virtual Machine for the Java language, the ASTI optimizer used in IBM’s XL Fortran product compilers, the PTRAN automatic parallelization system, and profile-directed partitioning and scheduling of Sisal programs. He is in the process of starting up three new research projects at Rice: the Habanero Virtual Machine project for homogeneous & heterogeneous multicore processors, optimization of high-productivity languages for high-end parallel systems, and foundations of program analysis and compilers for parallel software. Professor Sarkar became a member of the IBM Academy of Technology in 1995, an ACM Distinguished Scientist in 2006, and the E.D. Butcher Professor of Computer Science at Rice University in 2007. Prior to joining Rice University in July 2007, Professor Sarkar was Senior Manager of Programming Technologies at IBM Research. The projects under way in his department at IBM spanned the areas of 1) Programming Models and Language Design: PERCS/X10, XJ/DALI, Collage, 2) Programming Tools: Continuous Software Quality (including SAFE, Security Analysis, Scripting Analysis, WALA), PERCS Parallel Tools (including contributions to Eclipse Parallel Tools Platform), SAFARI, Advanced Refactoring, and 3) Deployment, Optimization and Execution: Metronome, PDS/Mirage, Jikes RVM. His responsibilities at IBM also included leading IBM's research efforts in Programming Model, Tools, and Productivity in the PERCS project during 2002 - 2007 as part of the DARPA-funded program on High Productivity Computing Systems. Professor Sarkar holds a B.Tech. degree from the Indian Institute of Technology, Kanpur, an M.S. degree from University of Wisconsin-Madison, and a Ph.D. from Stanford University. In 1997, he was on sabbatical as a visiting associate professor at MIT, where he was a founding member of the MIT RAW multicore project. |